In the field of integrated circuits there is an ongoing desire to reduce power dissipation. An obvious reason for such a desire is that energy is not free. Often, integrated circuits are combined into devices such as servers. Servers may operate in installations containing many such devices that operate twenty-four hours a day, seven days a week. In such a situation, energy costs can quickly escalate. Accordingly, circuit designers are continually seeking new ways to reduce power dissipation.
A not-so-apparent reason for seeking to reduce power dissipation is that power use in integrated circuits generates heat. Many such integrated circuits working together can generate a great deal of heat. If not handled properly, heat can have negative consequences for the operation of integrated circuits. Excessive heat can cause integrated circuits to fail prematurely, resulting in unforeseen maintenance and repair costs. Even if anticipated, excessive heat generation can have negative consequences by requiring complex designs incorporating cooling apparatus that also dissipate power.
Corporations and institutions responsible for energy costs are continually seeking devices that cost less to operate. One known technology to reduce power dissipation is called power gating. When logic circuitry that is capable of performing functional operations is not needed, power gating circuitry switches the power off to the logic circuitry.
Power gating logic circuits have been demonstrated to reduce standby leakage by greater than an order of magnitude in CMOS circuits. One typical method of power gating is to use a shared NFET (N-type field effect transistor) device as a power supply interrupt switch (footer). Sizing the footer presents challenges for the circuit designer; too large of a footer reduces the potential leakage savings, too small of a footer will cause a rise in the voltage of the virtual ground node (footer drain) and slow down the operation of the gated logic during the functional mode. Correct sizing is imperative to optimize the competing trade-offs. Sizing the footer correctly requires detailed knowledge of active power consumption, which is often not known accurately for a particular circuit at the time when the power-gating footer must be sized. Turn-on current transients also can cause ground bounce on the virtual ground node. These transients can be avoided by allowing extra “dead” cycles between sleep modes and functional operation, at the expense of system performance. However, introduction of extra “dead” cycles can result in inefficient operation since in some situations the dead cycles may be unnecessary.
Accordingly, those skilled in the art seek methods and apparatus that are capable of controlling integrated circuits incorporating power gating technology in such a manner that reacts to the dynamic conditions being experienced by the power gating circuitry. The prior art is not seen to appreciate the need for monitoring operating conditions associated with the power gating circuitry. A need therefore exists for apparatus and methods that can monitor the internal level of a virtual ground node associated with power gating circuitry. The apparatus preferably should be a low circuit area device with high sensitivity to small changes in the virtual ground level.